DocumentCode :
3178398
Title :
A 12-bit CMOS current steering D/A converter with a fully differential voltage output
Author :
Fu, Guoyuan ; Mantooth, H. Alan ; Di, Jia
Author_Institution :
Electr. Eng. Dept., Univ. of Arkansas, Fayetteville, AR, USA
fYear :
2011
fDate :
14-16 March 2011
Firstpage :
1
Lastpage :
7
Abstract :
This paper presents the design of a 12-bit 8MSamples/s (MSPS) current-steering digital-to-analog converter (DAC) using 0.13 μm CMOS technology. The proposed DAC has adopted a segmented architecture in order to achieve a minimized die area and optimized performance. The current steering network consists of binary weighted current sources for the 8 least significant bits (LSBs) and a unary current cell array for the 4 most significant bits (MSBs). A fully differential amplifier (FDA) is utilized in the design to provide differential voltage output, enable the DAC to work at ultra low supply voltages, and reduce harmonic distortion in the output. The simulation results of the extracted layout show a maximum INL and DNL of 0.17 LSB and 0.20 LSB, respectively. The mid-code glitch energy is 78 pV-s and the SFDR is 81.8 dB. The settling time of the DAC is 38.2 ns and the power consumption is 13.4 mW. The chip active area is 330 μm × 224 μm. The DAC performance has also been verified with a supply voltage down to as low as 0.72 V. To the best of our knowledge, this is the first demonstration of a DAC capable of working at such a low supply voltage. This DAC will be used in a bio-implantable system for medical applications.
Keywords :
CMOS analogue integrated circuits; cellular arrays; circuit optimisation; differential amplifiers; digital-analogue conversion; harmonic distortion; low-power electronics; 8MSamples; CMOS current steering D/A converter; CMOS technology; DAC performance; DNL; FDA; INL; LSB; MSB; MSPS current-steering digital-to-analog converter; SFDR; binary weighted current sources; bioimplantable system; current steering network; differential voltage output; fully differential amplifier; harmonic distortion; least significant bits; medical applications; midcode glitch energy; minimized die area; most significant bits; optimized performance; power 13.4 mW; power consumption; segmented architecture; size 0.13 mum; ultra low supply voltages; unary current cell array; word length 12 bit; CMOS integrated circuits; Computer architecture; Decoding; Layout; Resistors; Synchronization; Transistors; CMOS; Digital-to-analog converters; current-steering; fully differential output; segmentation; ultra low supply voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ISQED), 2011 12th International Symposium on
Conference_Location :
Santa Clara, CA
ISSN :
1948-3287
Print_ISBN :
978-1-61284-913-3
Type :
conf
DOI :
10.1109/ISQED.2011.5770757
Filename :
5770757
Link To Document :
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