Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops

In this paper, detailed analysis is given on the design of metastable-hardened and soft-error tolerant flip-flops while maintaining the basic characteristics of low-power and high-performance. We also propose two new flip-flop designs: pre-discharge soft-error tolerant flip-flop (PDFF-SE) and sense-amplifier transmission-gate soft-error tolerant flip-flop (SATG-SE). Following our main design approach, both PDFF-SE and SATG-SE use a cross-coupled inverter on the critical path in the master-stage to achieve good metastability while generating differential signals to facilitate the usage of the Quatro cell in the slave-stage to protect against soft-errors. PDFF-SE is designed to achieve very high performance with good metastability while SATG-SE is a low-power design also with good metastability. We also introduce two new design metrics, namely the metastability-delay-product (MDP) and the metastability-power-delay-product (MPDP), to analyze the design tradeoffs between metastability, power, and performance. Simulation results in 65 nm CMOS technology have shown that both proposed designs achieve significant reduction in MDP and MPDP when compared to other flip-flop architectures analyzed in this work. Monte Carlo simulation results also show that these flip-flops are very robust and reliable against process variations and mismatches.