Logic restructuring for MUX-based FPGAs

In this paper we present a logic restructuring tool for digital circuits implemented in MUX-based FPGAs. In this tool, logic optimization is achieved by incremental transformations of a mapped network. Working on a technology-dependent network allows to take into account accurate estimations of module count and delay of the circuit. The transformations are identified with the use of efficient Automatic Test pattern Generation (ATPG) based techniques that are able to operate directly on a structural circuit description. To this purpose, we have extended these techniques to the case of MUX-based FPGA mapped networks. Experimental results show that significant reduction in delay and module count can be obtained with this approach on the ACT1 architecture. This approach can be easily applied to other MUX-based architectures as well as post-layout delay optimization by directly using post-layout delay estimations