The effect of SRNR on timing characteristics of signal busses

At exceedingly high integration nodes and high signal transition frequencies, signal integrity (SI) is a major design concern. The main culprits are parasitics, capacitive and inductive, inherent in the circuit elements and interconnect. The Semi-Random Net Reordering (SRNR) technique concentrates on reducing the fundamental contributors to capacitive and inductive coupling in interconnect at the top-level of an integrated circuit´s design. By reducing overlap length and increasing separation distance, SRNR is able to improve signal timing characteristics in wide signal busses dramatically. A routing structure employing the SRNR technique is faster and more uniformly behaved compared to the same routing structure under standard routing methodology.