Test generation for gate oxide short in CMOS ICs

A GOS fault simulation program that gives the test coverage of GOS defects, given a set of test patterns, has been implemented. Generalized test patterns for GOS are developed for an AI gate. For each entry in the fault list, the test pattern to detect that fault, with all possible input gates, is considered, and a common test pattern is found with which the fault can be detected irrespective of the input logic. Generalized rules for detecting GOS in an OI gate, an AND gate, and an inverter are given. The generalized rules are formulated after iterating through all the possible input logic combinations. Results obtained for PFET and NFET showed symmetry in that the same conditions were obtained for all p-type transistors of the gate under test. This was also the case with the n-type transistors