A segmented gray code for low-power microcontroller address buses

The paper presents a novel approach to using the switching activity enhancements of a gray code on high capacitive microcontroller address lines. A novel segmented gray code is introduced that overcomes the exploding complexity disadvantage of higher bit width gray code incrementers compared to binary counters, by breaking down the global scope of the common gray code. A method is developed to evaluate all possible 4 bit gray codes by performing a synthesis of an incrementer for each of the 2687 valid codes. Resulting from this evaluation, a gray code is presented for which the area and power consumption of its incrementer is smaller than for a binary counter. This code, combined with the concept of the segmented gray code, used for a microprocessor program counter, leads to a decrease of the switching activity on the address bus by 25-30% as well as a decrease in the area and power consumption of the program counter by about 10%. Further, some considerations are given about branches, displacements and indexed addressing in a microprocessor architecture that intends to implement the presented segmented gray code program counter