Application-dependent testing of FPGA delay faults

To ensure correct operation of an FPGA based system with regard to timing characteristics, an application-dependent FPGA testing, i.e. testing of an FPGA programmed to implement a user-defined function, must be performed. We propose a procedure for application-dependent self testing of an in-circuit reprogrammable FPGA and develop BIST schemes that preserve the FPGA timing. For these schemes, the reconfiguration of a portion of the FPGA into test resources has no impact on the timing characteristics of that part of the FPGA which is currently being tested. We also present a method for enhancing the susceptibility of FPGA delay faults to random testing. It is based on modifying the functions of programmable logic components in the section under test. We compare the efficiency of the self-test scheme that uses this method with the earlier reported BIST techniques that rely on the design of test pattern generators best suited for pseudoexhaustive testing of delay faults