Timing yield estimation of carbon nanotube-based digital circuits in the presence of nanotube density variation and metallic-nanotubes

Carbon Nanotube Field Effect Transistors (CNFETs) show great promise to become successor of silicon CMOS because of its excellent electrical properties. However, CNFET-based circuits will face great fabrication challenges that will translate into imperfection and variability and lead to significant yield reduction. In this paper, we address the timing yield problem of CNFET-based sequential digital circuits. We propose an analytical approach to parametric timing yield prediction of CNFET-based circuits. In our approach, a statistical method is used to get the timing yield based on the delay distributions of register-to-register paths in a circuit with respect to carbon nanotube density variation and metallic-nanotubes. The superiority of the proposed technique is studied and verified against Monte Carlo simulation.