Analysis of within-die process variation in 65nm FPGAs

FPGAs are a great platform for studying within-die process variation because test structures can be implemented in product silicon using reconfigurable logic. This approach can achieve very high coverage without wasting otherwise useful silicon area. In this paper, we present a detailed analysis of within-die delay variation in a 65nm FPGA. We use densely distributed test oscillators to measure within-die performance variation across a large sample of dies, and identify both random and spatially correlated systematic components through post-processing. Finally, we evaluate the benefit of modeling within-die systematic variation in static timing analysis.