• DocumentCode
    3179460
  • Title

    Estimating the probability density function of critical path delay via partial least squares dimension reduction

  • Author

    Ben, Yu ; Spanos, Costas J.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA
  • fYear
    2011
  • fDate
    14-16 March 2011
  • Firstpage
    1
  • Lastpage
    7
  • Abstract
    We propose a method based on partial least squares (PLS) regression to estimate the probability density function of the critical path delay. The method works on a reduced problem facilitated by PLS regression and requires only 102 samples to achieve satisfactory accuracy. The method is verified by simulations on ISCAS´85 benchmark circuits.
  • Keywords
    delays; least squares approximations; logic circuits; logic gates; probability; regression analysis; ISCAS´85 benchmark circuits; PLS regression; critical path delay; digital logic block; logic gates; partial least squares dimension reduction; probability density function estimation; Delay; Estimation; Logic gates; Monte Carlo methods; Threshold voltage; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ISQED), 2011 12th International Symposium on
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1948-3287
  • Print_ISBN
    978-1-61284-913-3
  • Type

    conf

  • DOI
    10.1109/ISQED.2011.5770809
  • Filename
    5770809
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3179460