DocumentCode :
3179593
Title :
Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping
Author :
Meng, Kuo-Hsuan ; Pan, Po-Cheng ; Chen, Hung-Ming
Author_Institution :
Dept. of Electr. & Comput. Engr., Univ. of Illinois, Urbana, IL, USA
fYear :
2011
fDate :
14-16 March 2011
Firstpage :
1
Lastpage :
8
Abstract :
This work presents a synthesis framework for nanometer analog, mixed-signal, and radio-frequency circuit design. Our approach has both the advantages of accuracy and efficiency, accomplished by integrating both circuit simulator and analytic formulation. Through performance space exploration, this work facilitates optimal specification setting and trade-off aspect identification from nanometer technology nodes. The hierarchical global-to-local search process consists of device characterization, mapping from geometry-biasing parameters through circuit-level parameters to performance metrics, and reverse identification of optimal design variables with fine-tuning. The nature of hierarchy enables the capability of synthesizing large-scaled design with guarantee of accurate and fast convergence to the global optimum. Also this framework can be utilized to identify the constraints that are critically strict to the overall performance, such that the circuit can be designed to operate close to its limit. A radio-frequency distributed amplifier is synthesized as the demonstration showing that the proposed framework is effective and efficient.
Keywords :
analogue circuits; circuit simulation; distributed amplifiers; integrated circuit design; mixed analogue-digital integrated circuits; nanoelectronics; radiofrequency amplifiers; radiofrequency integrated circuits; circuit simulator; circuit-level parameter; fine-tuning; geometry-biasing parameter; hierarchical global-to-local search process; integrated hierarchical RF circuit synthesis; integrated hierarchical analog circuit synthesis; large-scaled design synthesis; mixed-signal circuit design; nanometer analog circuit design; nanometer technology nodes; performance mapping; performance metrics; radiofrequency circuit design; radiofrequency distributed amplifier; trade-off aspect identification; Equations; Integrated circuit modeling; Mathematical model; Optimization; Performance evaluation; Space exploration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ISQED), 2011 12th International Symposium on
Conference_Location :
Santa Clara, CA
ISSN :
1948-3287
Print_ISBN :
978-1-61284-913-3
Type :
conf
DOI :
10.1109/ISQED.2011.5770817
Filename :
5770817
Link To Document :
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