Microarchitectural synthesis of ICs with embedded concurrent fault isolation

In an increasing number of applications, reliability is essential. On-line resiliency when confronted with permanent faults is a difficult and important aspect of providing reliability. Particularly vexing is the problem of fault identification. Current methods are either domain specific or expensive. We have developed an approach to permanent fault isolation. In high-level synthesis that enables isolation through algorithmic application without necessitating complete functional unit replication. Fault identification is achieved through a unique binding methodology based on an extension of parity-like error correction equations in the domain of functional units. The result is an automated chip level approach with extremely low area and cost overhead.