A high speed reconfigurable integrated architecture for DWT

In this paper, we present an integrated systolic architecture for the discrete wavelet transform (DWT). This architecture is useful for both decomposition (forward DWT) and reconstruction (inverse DWT) of signals. The architecture has been designed based on an efficient systolic algorithm suitable for high speed VLSI implementation. This systolic architecture is unique in the sense that the same architecture is used for forward DWT and inverse DWT by selecting some suitable control signals and this systolic architecture yields 100% utilization unlike many other existing architectures in the literature. The two-dimensional DWT architecture can easily be designed by extending this one-dimensional solution