Title :
Technology of a depth-2 full-adder circuit using the InP RTD/HFET MOBILE
Author :
Prost, W. ; Auer, U. ; Degenhardt, J. ; Brennemann, A. ; Pacha, C. ; Goser, K.F. ; Tegude, F.J.
Author_Institution :
Dept. of Solid State Electron., Gerhard-Mercator-Univ. GH Duisburg, Germany
Abstract :
The technology of resonant tunneling device logic circuits using a modified monostable-bistable transition logic element (MOBILE) is presented. A nanoelectronic circuit architecture based on an improved MOBILE threshold logic gate is used. The improvements of the basic MOBILE are motivated from the circuit design point of view, and comprise a separate power supply and clock, a dual threshold voltage process, and on-chip clock delay lines. The demonstrator circuit is a pipelined one-bit full adder on an InP-substrate. SPICE simulations are carried-out in order to prove the functionality and to evaluate tolerable clock and supply voltage fluctuations in comparison to device parameter feasibility
Keywords :
III-V semiconductors; SPICE; adders; circuit simulation; clocks; field effect logic circuits; indium compounds; integrated circuit layout; logic design; nanotechnology; pipeline processing; resonant tunnelling diodes; threshold logic; InP; InP RTD/HFET MOBILE; InP-substrate; MOBILE threshold logic gate; SPICE simulations; circuit design; clock; clock fluctuations; depth-2 full-adder circuit; dual threshold voltage process; monostable-bistable transition logic element; nanoelectronic circuit architecture; on-chip clock delay lines; pipelined one-bit full adder; power supply; resonant tunneling device logic circuits; supply voltage fluctuations; Circuit synthesis; Clocks; HEMTs; Indium phosphide; Logic circuits; Logic devices; Logic gates; MODFETs; Power supplies; Resonant tunneling devices;
Conference_Titel :
Indium Phosphide and Related Materials, 2001. IPRM. IEEE International Conference On
Conference_Location :
Nara
Print_ISBN :
0-7803-6700-6
DOI :
10.1109/ICIPRM.2001.929099
