High Performance Sparse LU Solver FPGA Accelerator Using a Static Synchronous Data Flow Model

Sparse LU solvers are common in several scientific problems. The hardware utilization of previous implementations on massively parallel platforms never exceeded the 20% mark (including multicores, GPU, and FPGA). This is due to the highly irregular computation and memory access pattern of the algorithm. Reconfigurable fabrics, with its spatial execution model, can expose the maximum inherent parallelism in the problem and achieve the highest hardware utilization. However, dynamic data flow models implementations suffer from large overhead and scalability issues. In this paper, we propose a static dataflow synchronous model that maximizes the utilization of FPGA-based architectures. Synchronous dataflow graph is mapped to a mesh of deeply-pipelined PEs to perform the factorization. This inspires the development of a customized data structure format that reduces memory accesses, indexing overhead and pipelining hazards. The hardware model is synthesized on a VIRTEX 7 FPGA and the results show a hardware utilization exceeding 60%, which was translated to more than 100 GFLOPS.