Performance and Energy Optimization on MPSoCs by Enabling STT-MRAM LUTs

Increasing computation demands with limited power budget require more energy-efficient design without performance degradation in embedded systems and mobile computing platforms. Reconfigurable computing is an alternative to optimize both performance and power consumption. However, due to the complexity of hardware design, implementing dedicated accelerators usually lacks flexibility and productivity. In this work, our previous hybrid parallel co-design framework is extended. By using the partial reconfiguration technique, a dynamic reconfiguration scheme is presented to optimize both performance and power consumption without losing the programming flexibility. In addition, spin-torque transfer magneto resistive RAM (STT-MRAM) LUTs are exploited to replace traditional SRAM-based LUTs for further reducing the static power consumption. The results show that dynamic scheduling with hardware kernels implemented in STT-MRAM LUTs is 7.7 times better than the purely software implementation in terms of the product between the performance and the energy. Besides, when comparing STT-MRAM and SRAM hardware kernels, the STT-MRAM kernels have significant advantages over SRAM ones on the power consumption, especially the static power consumption.