• DocumentCode
    3181877
  • Title

    Reducing time by avoiding process serialisations in or-parallel interpretation of logic programs

  • Author

    Escalada-Imaz, G. ; Serres, F. Manyà

  • Author_Institution
    Artifical Intelligence Res. Inst., Univ. Autonoma de Barcelona, Spain
  • Volume
    5
  • fYear
    1995
  • fDate
    22-25 Oct 1995
  • Firstpage
    4539
  • Abstract
    Two kinds of parallelism arise when interpreting a logic program with a parallel architecture: Or-parallelism and And-parallelism. The former searches in parallel for the solution of one goal-literal by executing one process for each clause whose head unifies with the goal-literal. The latter is applied to solve the clause body activating parallel processes for the literals in the body of a clause. A big drawback of the previous Or-parallel models is that they fall down easily in the combinatorial explosion inherent in the solution of a logic programming problem. In this context, a particular processor in a parallel architecture is constrained to work with many processes which causes huge overheads by change contexts. The limitation in the required number of processes reduces the communication costs and it also avoids to serialise the processes
  • Keywords
    logic programming; parallel architectures; parallel machines; program interpreters; logic programming; or-parallel interpretation; parallel architecture; parallel interpreter; parallel processing; process serialisations; time reduction; Communication industry; Concurrent computing; Context; Costs; Councils; Electronic mail; Explosions; Logic programming; Parallel architectures; Parallel processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Systems, Man and Cybernetics, 1995. Intelligent Systems for the 21st Century., IEEE International Conference on
  • Conference_Location
    Vancouver, BC
  • Print_ISBN
    0-7803-2559-1
  • Type

    conf

  • DOI
    10.1109/ICSMC.1995.538510
  • Filename
    538510