• DocumentCode
    3182181
  • Title

    A 0.18 μm CMOS SoC of a front-end hardware platform for DVD-multi recorders

  • Author

    Kim, JooSeon ; Choi, GoangSeog ; Park, HyunJeoug ; Ahn, YoungJun ; Myungsik Kim ; Cho, KiSun ; Lee, TaeHo ; Han, MyungHee ; Bae, JumHan ; Park, HyunSoo ; Lee, YoonWoo ; Jung, SooYul ; Seo, JoongEon ; Shin, DongHo

  • Author_Institution
    Samsung Electron. Co., Suwon, South Korea
  • fYear
    2005
  • fDate
    8-12 Jan. 2005
  • Firstpage
    53
  • Lastpage
    54
  • Abstract
    This work presents a 0.18 μm CMOS system on a chip (SoC) that is a hardware platform for the front-end of DVD-multi recorders (FESOC). It has one 32 bit RISC CPU and one 16 bit DSP as well as most of the necessary components for DVD recorders, except for an analog front end (AFE) and some memories. The necessary building blocks are a partial response channel maximum likelihood detector (PRML), a servo signal processor (SERVO), write strategy controller (WSC), a data processor (DP), an AT-attachment packet interface (ATAPI), and a micro computer unit (MCU). Using a three-layered bus architecture enables this FESOC to work well with a 16 bit-wide bus at 67 MHz for 8× DVD operation, and to be implemented with a short development time. The FESOC is fabricated in 0.18 μm 1-poly 5-metal CMOS technology. It contains 8.4 million transistors in a 46 mm2 die and consumes 1.4 W with a channel clock of 209.28 MHz in 8× operation mode.
  • Keywords
    CMOS digital integrated circuits; digital signal processing chips; digital versatile discs; maximum likelihood detection; reduced instruction set computing; system-on-chip; 0.18 micron; 1.4 W; 16 bit; 209.28 MHz; 32 bit; 67 MHz; AT-attachment packet interface; ATAPI; CMOS SoC; DSP; DVD-multi recorder front-end hardware platform; FESOC; MCU; PRML; RISC CPU; SERVO; WSC; data processor; micro computer unit; partial response channel maximum likelihood detector; servo signal processor; triple-layered bus architecture; write strategy controller; CMOS technology; DVD; Detectors; Digital signal processing chips; Hardware; Maximum likelihood detection; Partial response channels; Reduced instruction set computing; Servomechanisms; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Consumer Electronics, 2005. ICCE. 2005 Digest of Technical Papers. International Conference on
  • Print_ISBN
    0-7803-8838-0
  • Type

    conf

  • DOI
    10.1109/ICCE.2005.1429713
  • Filename
    1429713