Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions

Although FPGA logic resources groups present some homogeneity, available Dynamic Partial Reconfiguration (DPR) tools consider them entirely heterogeneous. This assumption implies that each partial bit stream has to be allocated to one Reconfigurable Partition (RP). To solve this limitation, we present in this paper a new Assisted Design Flow (ADF) that implements a very efficient Partial Bit stream for Multiple Partitions (PB4MP) technique. Based on the Xilinx tools flow, the proposed ADF: takes advantage of the Xilinx tools constraints, does not require any intermediate manual steps, gives more freedom to the tools than similar approaches, and only repeats the regular flow once. Having the ability to disable all interface signals from each RP, this method allows to relocate modules safely in different RPs with the same bit stream or by an internal configuration memory swap, which increases system dependability and significantly facilitates the hardware tasks management.