Exploring the unified design-space of custom-instruction selection and resource sharing

Resource sharing can be applied during data-path synthesis of Instruction-Set Extensions (ISEs) in order to obtain flexibility and area efficiency. The design space of resource sharing solutions can be explored in order to find the trade-offs between area and instruction latency that suit the design goals. On the other hand, area is a proven global constraint that should be considered in the ISE selection process, since maximizing speedup as a unique goal assumes the availability of unlimited resources. Thus, a selection process should be aware of the area requirements of a subset of ISE candidates. However, when resource sharing is used for ISE data-path synthesis, the area and profitability of the subset cannot be known until resource sharing is attempted. This paper proposes a hardware/software partitioning framework in which the selection of ISEs interacts with the resource sharing process in order drive the exploration of the selection design space towards implementation alternatives that are likely to increase the utilization of the given area resources. On the benchmarks analyzed in this paper, our techniques find solutions that under a fixed area constraint, achieve speedups from 8% to 238% higher than previous selection techniques. Furthermore, unlike previous approaches, the proposed framework allows the exploration, at the selection level, of the design space of trade-offs between speedup and area that are available to the designer.