Title :
Design and Analysis of a High-speed Comparator in a Pipelined ADC
Author :
Yang, Wen-Rong ; Wang, Jia-Dong
Author_Institution :
Key Lab. of Adv. Display & Syst. Applic., Shanghai Univ., Shanghai
Abstract :
This paper presents a kind of high-speed voltage difference comparator. The comparator consists of preamplifier stage and dynamic latch with reset port. Based on standard 0.35 um/5 v CMOS process model, the circuit is simulated with Cadence EDA software. By analysis of circuit and EDA simulation, the comparator has the characteristics with high speed, good precision and low power dissipation. And it is suitable for the A/D converter with pipeline structure.
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; circuit simulation; comparators (circuits); high-speed integrated circuits; low-power electronics; CMOS process model; Cadence EDA software; circuit simulation; high-speed comparator design; high-speed voltage difference comparator; low power dissipation; pipelined ADC; preamplifier stage; reset port dynamic latch; size 0.35 mum; Analytical models; CMOS process; Circuit analysis; Circuit simulation; Electronic design automation and methodology; Latches; Preamplifiers; Semiconductor device modeling; Software standards; Voltage; ADC; analog-to-digital converters; comparator; high speed; pipelined;
Conference_Titel :
High Density packaging and Microsystem Integration, 2007. HDP '07. International Symposium on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-1252-8
Electronic_ISBN :
1-4244-1253-6
DOI :
10.1109/HDP.2007.4283625
