VLSI Implementation of CAVLC Decoder for H.264/AVC Video Decoding

This paper presents an efficient method of the contest- based adaptive variable length code (CAVLC) decoder for H.264/AVC standard. In the proposed design, according to the regularity of the codewords, the first 1 detector is used to solve the problem that the traditional method of table- searching has low efficiency. Considering the relevance of the data used in the process of RunBefore´s decoding, arithmetic operation is combined with FSM, which achieves higher decoding efficiency. The simulation result shows that the decoder can decode the coded stream of transform coefficients in each block. Moreover, it can decode every syntax element in one clock cycle. When the proposed design is synthesized at clock constraint of 100 MHz, the synthesis result shows that the design costs 9600 cells under a 0.25 mum CMOS technology, which meets the demand of real time decoding in H.264/AVC standard.