Design space exploration of instruction set customizable MPSoCs for multimedia applications

Multiprocessor System-on-Chips or MPSoCs in the embedded systems domain are increasingly employing multiple customizable processor cores. Such cores offer higher performance through application-specific instruction-set extensions without sacrificing the flexibility of software solutions. Existing techniques for generating appropriate custom instructions for an application domain are primarily restricted to specializing a single processor with the objective of maximizing performance. In a customizable MPSoC, in contrast, the different processor cores have to be customized in a synergistic fashion to create a heterogeneous MPSoC solution that best suits the application. Moreover, such a platform presents conflicting design tradeoffs between system throughput and on-chip memory/logic capacity. In this paper, we propose a framework to systematically explore the complex design space of customizable MPSoC platforms. In particular, we focus on multimedia streaming applications, as this class of applications constitutes a primary target of MPSoC platforms. We capture the high variability in execution times and the bursty nature of streaming applications through appropriate mathematical models. Thus, our framework can efficiently and accurately evaluate the different customization choices without resorting to expensive system-level simulations. We perform a detailed case study of an MPEG encoder application with our framework. It reveals design points with interesting tradeoffs between silicon area requirement for the custom instructions and the on-chip storage for partially-processed video data, while ensuring that all the design points strictly satisfy required QoS guarantees.