A parallel multimedia processor for macroblock based compression standards

Author

Mattavelli, M. ; Brunetton, S. ; Mlynek, D.

Author_Institution

Integrated Syst. Center, Fed. Inst. of Technol., Switzerland

Volume

2

fYear

1997

fDate

26-29 Oct 1997

Firstpage

570

Abstract

This paper presents a multimedia processor based on a SIMD architecture optimized for block-based video processing algorithms. The processor, called DGP (digital generic processor), is a generic system architecture, constituted by an array of pixel processors (SIMD) and a RISC controller. It is able to execute various video processing algorithms such as digital filtering, video effects, window clipping, and to perform video compression according to standards such as H.261, H.263, MPEG-1 and MPEG-2. The processor can be programmed in order to run the code corresponding to each specific algorithm

Keywords

CMOS digital integrated circuits; data compression; digital signal processing chips; parallel architectures; reduced instruction set computing; telecommunication standards; video coding; video signal processing; 0.5 micron; 1.7 GIPS; 54 MHz; DGP; H.261; H.263; MPEG-1; MPEG-2; RISC controller; SIMD architecture; block-based video processing algorithms; code; digital filtering; digital generic processor; generic system architecture; macroblock based compression standards; parallel multimedia processor; pixel processors; video compression; video effects; video processing algorithms; window clipping; Arithmetic; Computer architecture; Control systems; Decoding; Digital filters; Engines; Filtering algorithms; Process control; Reduced instruction set computing; Registers; Transform coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing, 1997. Proceedings., International Conference on

Conference_Location

Santa Barbara, CA

Print_ISBN

0-8186-8183-7

Type

conf

DOI

10.1109/ICIP.1997.638835

Filename

638835