n-Bit multiple read and write FIFO memory model for network-on-chip

Network-on-chip (NoC) architecture provides the communication infrastructure for system-on-chip (SoC) design. The architecture, size, and algorithm dominate the performance of NoC and influence on the design of arbiters in the switch. FIFO buffers are essential components of network switches-buffers have been estimated to be the single largest power consumer for a typical switch in an on-chip network. The buffer plays an important role in the design of MPSoC. The buffer mechanism influences the efficiency of link bandwidth. The buffer also provides a mechanism to synchronize the speed between the routers. The paper investigates available techniques for buffer design in NoC. Finally, we present a design of synchronous FIFO memory that could perform multiple read and write operation. We have also incorporated full and AlmostFull signal to avoid overflow. The proposed architecture of FIFO is implemented in RTL model using Verilog language. The FIFO has achieved a maximum operation frequency 366 MHz on Xilinx vertex device.