PHAFS: A parallel hardware accelerator for switch level fault simulation

Author

Ryan, Christopher A. ; Tront, Joseph G.

Author_Institution

Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA

fYear

1993

fDate

4-7 Apr 1993

Firstpage

0.625

Abstract

Existing fault simulation techniques have a worst-case computational complexity of O(n**2), where n is the number of devices in the circuit. A parallel hardware accelerated fault simulator (PHAFS) has been proposed in order to reduce the complexity to O(L**2), where L is the number of levels of switches encountered when traversing from output to input. An overview of the PHAFS architecture and system is presented. The PHAFS hardware component uses a massively parallel SIMD (single instruction, multiple data) architecture based on an application specific integrated circuit to perform two-dimensional parallel switch level fault simulation up to 32 switches and 192 faults

Keywords

application specific integrated circuits; circuit analysis computing; computational complexity; fault diagnosis; integrated circuit testing; logic testing; parallel architectures; PHAFS; application specific integrated circuit; massively parallel SIMD architecture; single instruction multiple data; switch level fault simulation; worst-case computational complexity; Circuit faults; Circuit simulation; Computational modeling; Computer simulation; Hardware; Integrated circuit modeling; Software prototyping; Switches; Switching circuits; Upper bound;

fLanguage

English

Publisher

ieee

Conference_Titel

Southeastcon '93, Proceedings., IEEE

Conference_Location

Charlotte, NC

Print_ISBN

0-7803-1257-0

Type

conf

DOI

10.1109/SECON.1993.465736

Filename

465736