Design and implementation of a neural network building block

Author

Schalkoff, R.J. ; Turner, A.E. ; Singh, R. ; Poole, K.F. ; King, S. ; Pillay, S. ; Reddy, G.S.

Author_Institution

Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA

fYear

1993

fDate

4-7 Apr 1993

Firstpage

0.708333333333333

Abstract

A hierarchical connectivity scheme for implementing a totally connected artificial neural network (ANN) is presented. An ANN chip unit (ACU) is the basic building block that implements a 16-input/output net, and the system is easily expandable to a 256-input/output network. The chip uses on-chip static random-access memory (SRAM) for storing weights to reduce off-chip time delays and takes advantage of a large and fast internal bus structure to move weights. The technology exploits InP for its high-speed multipliers and multichip module (MCM) packaging for interconnecting the ACUs

Keywords

SRAM chips; multichip modules; multiplying circuits; neural chips; ANN chip unit; InP; SRAM; artificial neural network; hierarchical connectivity scheme; high-speed multipliers; internal bus structure; multichip module; neural network building block; off-chip time delays; packaging; static random-access memory; Artificial neural networks; Computer networks; Delay effects; Indium phosphide; Large-scale systems; Network-on-a-chip; Neural networks; Random access memory; Registers; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Southeastcon '93, Proceedings., IEEE

Conference_Location

Charlotte, NC

Print_ISBN

0-7803-1257-0

Type

conf

DOI

10.1109/SECON.1993.465747

Filename

465747