A two-dimensional model at low-temperature for buried channel NMOS

Author

Ghazavi, Parvis ; Ho, F.D.

Author_Institution

Dept. of Electr. & Comput. Eng., Alabama Univ., Huntsville, AL, USA

fYear

1993

fDate

4-7 Apr 1993

Firstpage

0.666666666666667

Abstract

A two-dimensional simulation program has been developed to model in detail the behavior of depletion-mode MOSFETs from liquid-nitrogen temperature (77 K) to room temperature (300 K). The differences between the low-temperature model and the room-temperature model in terms of numerical approaches are discussed. Simulation results in the linear region (VDS = 0.1 V) for applied gate voltages at subthreshold and above threshold are reported. These results are in reasonable agreement with experimental data available in the literature. Simulation results on the saturation region for a typical depletion-mode NMOS transistor are also presented

Keywords

MOSFET; circuit analysis computing; semiconductor device models; 77 to 300 K; buried channel NMOS; depletion mode MOSFET; depletion-mode NMOS transistor; experimental data; gate voltage; linear region; liquid-nitrogen temperature; low-temperature model; numerical approaches; room temperature; room-temperature model; saturation region; simulation results; subthreshold; threshold; two-dimensional model; two-dimensional simulation program; Charge carrier processes; Computational modeling; Doping; MOS devices; MOSFETs; Numerical models; Poisson equations; Statistics; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Southeastcon '93, Proceedings., IEEE

Conference_Location

Charlotte, NC

Print_ISBN

0-7803-1257-0

Type

conf

DOI

10.1109/SECON.1993.465750

Filename

465750