On reusability of verification assertions for testing

Assertions have proven to be an effective mechanism to improve quality and to speed-up simulation-based design verification. They are created and embedded to the simulatable design description by the designer, the person with the deepest knowledge about the desired functionality and its real implementation. In this paper we propose to reuse this valuable information during the design manufacturing testing phase to increase the test quality and efficiency. The paper considers different types of design properties created for verification such as environmental assumptions and internal signal assertions. The reusable information is proposed to be applied for test pattern generation, embedded test observability improvement and DfT (design for testability) enhancement.