Title :
Architectural exploration tasks for on-chip embedded systems
Author :
Reinsalu, Uljana ; Arhipov, Anton ; Ellervee, Peeter
Author_Institution :
Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn
Abstract :
In this paper an idea is proposed, how to simulate a large digital system that could not be mapped onto single FPGA, utilizing the sate-of-the-art features of modern reconfigurable devices. Partial reconfiguration of these devices is the feature for the idea described. Methodology of design flow to any platform is proposed and main problems concerning this methodology are highlighted.
Keywords :
embedded systems; field programmable gate arrays; logic design; reconfigurable architectures; system-on-chip; FPGA; architectural exploration task; design flow methodology; large digital system; on-chip embedded system; reconfigurable device; Cryptography; Databases; Design methodology; Embedded system; Emulation; Hardware; Iterative algorithms; Libraries; Sorting; System-on-a-chip;
Conference_Titel :
Electronics Conference, 2008. BEC 2008. 11th International Biennial Baltic
Conference_Location :
Tallinn
Print_ISBN :
978-1-4244-2059-9
Electronic_ISBN :
1736-3705
DOI :
10.1109/BEC.2008.4657506
