DocumentCode
3186338
Title
Architectural exploration tasks for on-chip embedded systems
Author
Reinsalu, Uljana ; Arhipov, Anton ; Ellervee, Peeter
Author_Institution
Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn
fYear
2008
fDate
6-8 Oct. 2008
Firstpage
171
Lastpage
174
Abstract
In this paper an idea is proposed, how to simulate a large digital system that could not be mapped onto single FPGA, utilizing the sate-of-the-art features of modern reconfigurable devices. Partial reconfiguration of these devices is the feature for the idea described. Methodology of design flow to any platform is proposed and main problems concerning this methodology are highlighted.
Keywords
embedded systems; field programmable gate arrays; logic design; reconfigurable architectures; system-on-chip; FPGA; architectural exploration task; design flow methodology; large digital system; on-chip embedded system; reconfigurable device; Cryptography; Databases; Design methodology; Embedded system; Emulation; Hardware; Iterative algorithms; Libraries; Sorting; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Conference, 2008. BEC 2008. 11th International Biennial Baltic
Conference_Location
Tallinn
ISSN
1736-3705
Print_ISBN
978-1-4244-2059-9
Electronic_ISBN
1736-3705
Type
conf
DOI
10.1109/BEC.2008.4657506
Filename
4657506
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