An optimized structure CMOS dual-modulus prescaler using dynamic circuit technique

An optimized structure CMOS divide-by-128/129 or 64/65 dual-modulus prescaler using a dynamic circuit technique is implemented in 0.25 μm CMOS digital technology. The new optimized structure reduces the propagation delay and improves the operating speed. In this structure, an improved dynamic D-flipflop (DFF) is utilized. A prototype is fabricated and the measured results show that this prescaler works well in the Gigahertz frequency range. It only consumes 35 mW (including three power-hungry output buffers) when the input frequency is 2.5 GHz and the power supply voltage is 2.5 V. The die size is 0.47×0.46 mm².