Title :
An optimized structure CMOS dual-modulus prescaler using dynamic circuit technique
Author :
Chi, Baoyong ; Shi, Bingxue
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
An optimized structure CMOS divide-by-128/129 or 64/65 dual-modulus prescaler using a dynamic circuit technique is implemented in 0.25 μm CMOS digital technology. The new optimized structure reduces the propagation delay and improves the operating speed. In this structure, an improved dynamic D-flipflop (DFF) is utilized. A prototype is fabricated and the measured results show that this prescaler works well in the Gigahertz frequency range. It only consumes 35 mW (including three power-hungry output buffers) when the input frequency is 2.5 GHz and the power supply voltage is 2.5 V. The die size is 0.47×0.46 mm2.
Keywords :
CMOS digital integrated circuits; flip-flops; frequency dividers; prescalers; 0.25 micron; 2.5 GHz; 2.5 V; 35 mW; CMOS digital technology; CMOS dual-modulus prescaler; RF systems; dynamic D-flipflop; dynamic circuit technique; frequency dividers; frequency synthesizers; input frequency; operating speed; optimized structure; output buffers; power supply voltage; propagation delay; CMOS digital integrated circuits; CMOS technology; Counting circuits; Frequency conversion; Frequency measurement; Frequency synthesizers; Power supplies; Propagation delay; Prototypes; Voltage;
Conference_Titel :
TENCON '02. Proceedings. 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering
Print_ISBN :
0-7803-7490-8
DOI :
10.1109/TENCON.2002.1180313