Pave Pillar in-house research final report

Author

Blair, Jesse Lee ; Powers, Philip

Author_Institution

Wright Lab., Wright-Patterson AFB, OH, USA

fYear

1992

fDate

18-22 May 1992

Firstpage

193

Abstract

The authors report on the concepts and technologies required to develop, integrate, and test the Pave Pillar architecture in an avionics system. Hardware and software issues relating to multiprocessing, multitasking, and real-time reconfiguration are discussed. The issues involved in developing and integrating the VHSIC avionic modular processors (VAMPs), high-speed data bus networks, and Ada software are examined. An avionic hot bench simulation was integrated to provide a closed-loop real-time test set-up called the integrated testbed (ITB) facility. The configuration and test setup for the common avionics modules were selected to provide a realistic environment and to be as close to the defined Pave Pillar architecture as possible

Keywords

Ada; aerospace computing; aerospace test facilities; aircraft instrumentation; automatic test equipment; computer architecture; computerised instrumentation; digital simulation; military computing; military standards; military systems; multiprocessing systems; system buses; Ada software; Pave Pillar architecture; Pave Pillar in-house research; VHSIC avionic modular processors; avionic hot bench simulation; closed-loop real-time test; high-speed data bus networks; integrated testbed; multiprocessing; multitasking; real-time reconfiguration; Aerospace electronics; Aircraft; Computational modeling; Computer architecture; Computer displays; Computer simulation; Hardware; Software testing; System testing; Very high speed integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace and Electronics Conference, 1992. NAECON 1992., Proceedings of the IEEE 1992 National

Conference_Location

Dayton, OH

Print_ISBN

0-7803-0652-X

Type

conf

DOI

10.1109/NAECON.1992.220646

Filename

220646