True 50% duty-cycle high-speed divider with the modulus of odd numbers

Author

Tseng, Sheng-Che ; Wei, Hung-Ju ; Syu, Jin-Siang ; Meng, Chinchun ; Tsun, Kuan-Chang ; Huang, Guo-Wei

Author_Institution

Dept. of Commun. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2009

fDate

7-10 Dec. 2009

Firstpage

305

Lastpage

308

Abstract

This paper proposes a true 50% duty-cycle high-speed prescaler with an odd modulus, based on current switchable D flip-flops. Each D flip-flop can sample data at the positive and negative clock edges, because of the changeable trigger mode. The proposed divide-by-N prescaler, with a 50% duty cycle, is formed as a ring with an N number of D flip-flops. Two types of 50% duty-cycle divide-by-five prescalers, the sample-hold-sample-hold-hold (SHSHH) prescaler and the sample-sample-hold-sample-hold (SSHSH) prescaler, are implemented using the 0.35 Â¿m SiGe HBT technology. The SHSHH divider has a better performance, up to 7 GHz, thanks to the synchronization of data and control signals.

Keywords

Ge-Si alloys; dividing circuits; flip-flops; heterojunction bipolar transistors; prescalers; semiconductor materials; synchronisation; HBT technology; SiGe; data synchronization; duty-cycle high-speed divider; odd modulus; positive clock edges; sample-hold-sample-hold-hold prescaler; size 0.35 mum; switchable D flip-flops; Circuits; Clocks; Flip-flops; Frequency conversion; Germanium silicon alloys; Heterojunction bipolar transistors; Logic; Signal generators; Silicon germanium; Switches; 50% duty cycle; SiGe HBT; divide-by-N; prescaler;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2009. APMC 2009. Asia Pacific

Conference_Location

Singapore

Print_ISBN

978-1-4244-2801-4

Electronic_ISBN

978-1-4244-2802-1

Type

conf

DOI

10.1109/APMC.2009.5385392

Filename

5385392