Title :
Rapid migration to VLSI
Author :
Lowinski, W.B. ; Kirwan, R. ; Perry, A. ; Yu, T.
Abstract :
The use of design tools to create a 115,000-gate equivalent array within three generations is described. The first generation consisted of a 7800-gate equivalent array containing the glue logic for a dual redundant serial bus and was housed in a 120-pin ceramic pin grid array (PGA). CAE work stations are used for the creation of the design, and vendor-specific tools are used for final simulations. The second generation fully embedded the PGA into the array to support an Intel 80960 CPU. The second-generation ASIC was housed in a 256-pin quad flat pack (QFP) and was created on work stations utilizing vendor-specific tools. The third generation, a 115,000-gate equipment array, added a second PGA, three universal asynchronous receiver transmitters (UARTs), and two synchronous data-link control serial ports permitting the creation of a stand-alone computer I/O card in a single assembly
Keywords :
VLSI; application specific integrated circuits; circuit CAD; computer interfaces; engineering workstations; integrated logic circuits; logic CAD; ASIC; CAE work stations; Intel 80960 CPU; UARTs; VLSI; ceramic pin grid array; dual redundant serial bus; first generation; glue logic; logic gates; military standards; quad flat pack; second generation; simulations; synchronous data-link control serial ports; third generation; universal asynchronous receiver transmitters; vendor-specific tools; Application specific integrated circuits; Assembly; Ceramics; Computer aided engineering; Electronics packaging; Logic arrays; Mesh generation; Synchronous generators; Transmitters; Very large scale integration;
Conference_Titel :
Aerospace and Electronics Conference, 1992. NAECON 1992., Proceedings of the IEEE 1992 National
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-0652-X
DOI :
10.1109/NAECON.1992.220662
