DocumentCode
3186900
Title
Translation of digital designs in CMOS to gallium arsenide
Author
Howell, Gene E.
Author_Institution
Defense Electronics Supply Center, Dayton, OH, USA
fYear
1992
fDate
18-22 May 1992
Firstpage
90
Abstract
A methodology for translating a CMOS digital design to a GaAs digital design is described. Risks in the process are highlighted. Logic elements translated include simple gates (AND, OR, NOR) and a full adder. Test chips were successfully designed using this approach. A process test chip was tested, with results comparable to HSPICE model parameters obtained from Vitesse Semiconductor. The test chips were packaged in 52-pin LDCC/LCC packages
Keywords
CMOS integrated circuits; III-V semiconductors; SPICE; VLSI; circuit CAD; gallium arsenide; integrated logic circuits; logic CAD; packaging; AND; CMOS; GaAs; HSPICE model; LDCC/LCC packages; NOR; OR; VLSI; Vitesse Semiconductor; adder; digital designs; logic CAD; process test chip; CMOS technology; Circuit testing; Gallium arsenide; Integrated circuit packaging; Integrated circuit technology; Logic devices; MESFETs; Semiconductor device packaging; Semiconductor device testing; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Aerospace and Electronics Conference, 1992. NAECON 1992., Proceedings of the IEEE 1992 National
Conference_Location
Dayton, OH
Print_ISBN
0-7803-0652-X
Type
conf
DOI
10.1109/NAECON.1992.220663
Filename
220663
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