Title :
Fault simulation of interconnect opens in digital CMOS circuits
Author_Institution :
Design Center, Hewlett-Packard Co., CA, USA
Abstract :
We describe a highly accurate but efficient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations for the site of the open; using logic simulation for the rest of the circuit; taking four different factors, that can affect the voltage of an open, into account; and considering the oscillation and sequential behaviour potential of opens. A novel test technique based on controlling the die surface voltage is also described. We present simulation results of ISCAS85 layouts using stuck-at and IDDQ test sets.
Keywords :
CMOS digital integrated circuits; SPICE; circuit CAD; circuit analysis computing; integrated circuit testing; logic CAD; IDDQ test sets; ISCAS85 layouts; SPICE; die surface voltage; digital CMOS circuits; fault simulation; interconnect opens; logic simulation; standard cell library; stuck-at; transistor charge equations; Circuit simulation;
Conference_Titel :
Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-8200-0
DOI :
10.1109/ICCAD.1997.643593
