Title :
A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register
Author :
Darus, Zahari M. ; Ahmed, Iftekhar ; Ali, Md Liakot
Author_Institution :
Dept. of Electr., Electron. & Syst. Eng., Univ. Kebangsaan, Malaysia
Abstract :
This paper presents the design of a low cost, test processor ASIC chip implementing multiple seed, multiple polynomial linear feedback shift register (MPMSLFSR). User programmable seed and feedback connection can be set in the pattern generator of the chip to improve fault coverage. The ASIC also supports scan-path testing. It can also be used to design external IC tester
Keywords :
shift registers; ASIC chip; external IC tester; fault coverage; multiple polynomial linear feedback shift register; multiple seed; pattern generator; scan-path testing; simulation; test processor chip; Application specific integrated circuits; Circuit faults; Circuit testing; Costs; Feedback; Integrated circuit testing; Nonlinear equations; Polynomials; System testing; Test pattern generators;
Conference_Titel :
Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian
Conference_Location :
Akita
Print_ISBN :
0-8186-8209-4
DOI :
10.1109/ATS.1997.643952
