Parallelization of computer vision algorithms on a reconfigurable multiprocessor

A novel reconfigurable architecture based on a multi-ring multiprocessor network is described. The reconfigurable architecture is shown to combine low network diameter with a low degree of connectivity for each node in the network. The mathematical properties of the network topology and the hardware for the reconfiguration switch are described. Primitive parallel operations on the network topology are described and analyzed. A large class of algorithms for the Boolean n-cube and the 2-D mesh is shown to map efficiently on the proposed architecture without loss of performance. The architecture is shown to be well suited for a number of problems in computer vision