DocumentCode
3188751
Title
A 2.5-Gb/s clock and data recovery circuit with a 1/4-rate linear phase detector
Author
Alavi, S.M. ; Shoaei, O.
Author_Institution
IC Design Center, Tehran Univ., Iran
fYear
2005
fDate
13-15 Dec. 2005
Abstract
A 2.5-Gb/s phase-lock clock and data recovery (CDR) circuit is proposed in system simulation for SONET OC-48 (2.488/2.666-Gb/s) transceiver applications. The CDR circuit exploits 1/4-rate linear phase detector. Making use of this technique the design of voltage controlled oscillator (VCO) facilitates and also it eliminates 1:4 demultiplexer and frequency divider since this topology directly produces recover data.
Keywords
SONET; clocks; demultiplexing equipment; frequency dividers; integrated circuit design; phase detectors; synchronisation; transceivers; voltage-controlled oscillators; 2.5 Gbit/s; SONET OC-48; clock and data recovery; demultiplexer; frequency divider; linear phase detector; phase-lock clock circuit; transceiver applications; voltage controlled oscillator; Circuit simulation; Clocks; Detectors; Frequency conversion; Optical transmitters; Phase detection; Power dissipation; SONET; Transceivers; Voltage-controlled oscillators; 1/4 - rate clock; Clock and data recovery; OC-48; SONET; linear phase detector; voltage-controlled oscillator (VCO);
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2005. ICM 2005. The 17th International Conference on
Print_ISBN
0-7803-9262-0
Type
conf
DOI
10.1109/ICM.2005.1590037
Filename
1590037
Link To Document