Design of merged differential cascode voltage switch with pass-gate (MDCVSPG) logic for high-performance digital systems

Author

Majidzadeh, V. ; Alavi, S.M. ; Afzali-Kusha, A.

Author_Institution

IC Design Center, Tehran Univ., Iran

fYear

2005

fDate

13-15 Dec. 2005

Abstract

In this paper, a new high performance yet low power circuit technique called merged differential cascode voltage switch with pass-gate (MDCVSPG) is introduced. It combines the benefits of two logic styles of EDCVSL and DCVSPG. To verify the efficiency of the proposed logic, gates NAND, NOR, and XOR for the logic styles are simulated using HSPICE. The results show better performance and lower power consumption for MDCVSPG compared to EDCVSL and DCVSPG. In addition, when is used in design of an 8 bit ripple carry adder, the proposed style consumes 38% less silicon area compared to DCVSPG. The area efficiency is due to a reduction of transistor number and layout complexity.

Keywords

SPICE; adders; carry logic; circuit layout; circuit simulation; logic circuits; logic design; logic gates; low-power electronics; DCVSPG; EDCVSL; HSPICE; NAND; NOR; XOR; circuit layout; logic gates; logic styles; low power circuit technique; merged differential cascode voltage switch with pass-gate; power consumption; ripple carry adder; Adders; Circuit simulation; Digital systems; Energy consumption; Logic design; Logic gates; Silicon; Switches; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2005. ICM 2005. The 17th International Conference on

Print_ISBN

0-7803-9262-0

Type

conf

DOI

10.1109/ICM.2005.1590038

Filename

1590038