Dynamic Traffic Adaptable Switch

In computer networks, switches are used for interconnecting plurality of nodes for data exchange usually employs either single back plane or cross-bar bus architecture. Single back plane bus is limited by latency whereas cross-bar bus architecture comparatively requires more silicon space. The single bus is subjected to the entire load of the switch and at the same time it cannot support concurrent communication corresponding to multiple requests, results in waiting time causes abbreviation in throughput. The proposed solution introduces an ASIC (Application Specific Integrated Circuit) to determine the traffic condition over a period of time and corresponding to that it controls a section of MOSFET (Metal Oxide Semiconductor Field Effect Transistors) switches, connecting plurality of switch port to plurality of bus. The switch ports are grouped together in a manner such that each group encompasses only those switch ports which have preeminence communication among them. Each group of switch ports is mapped to discrete bus. A bridge is used to interconnect plurality of bus and contentions are resolved by a local and a central arbiter.