Low power embedded DRAMs with high quality error correcting capabilities

Embedded memories are part of almost any embedded system. To ensure an error free operation, error detecting/correcting codes or alternative schemes for on-line consistency checking can be used. The trade-offs with respect to error detection capabilities and hardware cost has been investigated in previous work. However, very often embedded systems also have to work with small batteries (e.g. mobile devices), and power consumption becomes a second crucial issue. In this paper a low power design for on-line consistency checking is proposed. The proposed scheme is analyzed with respect to its power consumption and compared to error detecting/correcting schemes based on error correcting codes. The results show that on-line consistency checking based on the modulo-2 address characteristic can ensure both low error detection latencies and reduced power consumption in contrast to alternative schemes.