Considerations for fault-tolerant network on chips

According to International Technology Roadmap for Semiconductors (ITRS), before the end of this decade we will be entering the era of a billion transistors on a single chip. However, it has been observed that as the system grows, so does the complexity of integrating various components on a chip. The major threat toward the achievement of a billion transistor chip is poor scalability of current interconnect structure of today\´s SoCs as presented by Benini and De Michelli (2002). In order to cope with growing interconnect infrastructure, the "network on chip (NoC)" concept was introduced. With network methodologies coming on-chip, various characteristics of traditional networks come into play. So far, failures that are common in regular networks were hardly considered on-chip; this paper introduces ideas of dynamic routing and congestion control in the context of NoCs and explains how they could be applied to cope with adverse physical effects of deep sub-micron technology.