VLSI Architecture & Implementation of H.264 Integer Transform

This paper describes the VLSI design & implementation of transform & quantization module for H.264/AVC. The proposed design aims has the capability of adaptively controlling the computational complexity. Integer transform architecture is proposed for taking 4×4 pixels blocks of residual video data as an input. The 4×4 integer transform is further reduced to two 2×2 sub-transforms. The two 2×2 matrix operations are performed in parallel thus satisfying the pipeline architecture which makes it more efficient. The multiplications in the transform operation are performed by simple left-shift operations while the division operation in the quantization process is achieved through right-shift operation. Using Xilinx® Vertex-2 FPGA technology, the logic gate count is only 4524, critical path delay is 8.104ns, output delay is only 22 clock cycles, & the maximum operational frequency is 127MHz.