Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels

In this paper we first observe that the required amount of compressed test data transferred from the tester to the embedded cores in a system-on-a-chip (SOC) varies significantly during the testing process. This motivates a new approach to test data compression, mainly applicable to core-based SOCs, based on time-multiplexing the tester channels through which the on-chip decompressors will receive compressed test data only when necessary. The distinguishing advantage of this approach is that it is suitable for concurrent testing of multiple cores in an SOC and not only will the volume of test data be reduced but also the tester channel utilization will be increased.