A Fault Tolerant On-Line Bisted SRAM IP-Core

Memory modules, as either devices or IP cores, appeared as one of the most critical parts in digital systems. The design of an efficient online memory BIST with low hardware overhead was always a goal for BIST designers, however having a fault tolerant BIST and reliable BIST architecture is one important issue that if neglected can make the whole BIST architecture useless. This paper presents a design approach for an on-line BIST architecture with fault tolerant ability for the SRAM IP-cores, which also has a respectful fault tolerant and data safety reliability. Proposed design has a low hardware overhead in contrast with the previous ones. Proposed architecture can guarantee the on-line BIST at the presence of a fault in the spare registers, used to keep a copy of source data of the under test memory cell. The optimum number of extra registers has been calculated which can guarantee 99% correcting ability.