Digital I/Q RF transmitter using time-division duplexing

We propose a digital I/Q transmitter architecture that avoids area, complexity, noise, distortion and linearity issues of the existing solutions by allocating separate time slots to the I and Q operations during which the respective digitally-controlled RF-switched resistors, realized as arrays of MOS switches, are active. This way, the operational orthogonality of the I and Q paths is maintained and the I/Q switch arrays can be simply connected together. An example silicon realization in 65 nm CMOS uses 25% duty cycle I/Q clocks.