Title :
A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation
Author :
Feygin, G. ; Nagaraj, K. ; Chattopadhyay, R. ; Herrera, R. ; Papantonopoulos, I. ; Martin, D. ; Wu, P. ; Pavan, S.
Author_Institution :
Texas Instrum., Warren, NJ, USA
Abstract :
A 8-bit A/D converter using an efficient architecture is described. An important feature of this is a background offset cancellation scheme. This A/D converter has been implemented in a 0.18 μm digital CMOS technology. It operates at up to 165 MS/s with an SNDR of 43.5 dB, a DNL of 0.7 LSB and an INL of 1 LSB. It occupies an active area of 0.9 mm2 and has a power dissipation of 140 mW
Keywords :
CMOS integrated circuits; analogue-digital conversion; 0.18 micron; 140 mW; 43.5 dB; 8 bit; CMOS A/D converter; CMOS ADC; background offset cancellation; digital CMOS technology; CMOS technology; Circuits; Clocks; Detectors; Instruments; Power dissipation; Resistors; Signal resolution; Video signal processing; Voltage;
Conference_Titel :
Custom Integrated Circuits, 2001, IEEE Conference on.
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-6591-7
DOI :
10.1109/CICC.2001.929745
