System considerations for wireless capacitive chip-to-chip signaling

Using capacitive-based chip-to-chip signaling in large-scale systems offers an interesting tradeoff between design and packaging complexity versus power consumption and performance. Placing chips together in close proximity offers low energy-per-bit costs and high I/O density, and therefore enables off-chip bandwidth levels far beyond those offered by traditional packaging and I/O technologies. Much of the previous published work on capacitive Proximity I/O has focused on mechanical methods for accurate chip alignment. In this paper we discuss some system design considerations unique to Proximity I/O. First, we compare and contrast circuit and layout techniques that optimize signal-to-noise ratio under expected chip misalignments. Next, we evaluate methods for establishing appropriate DC bias levels across a chip-to-chip capacitive link. Finally, we show a full Proximity I/O implementation to enumerate the required system overheads for clocking and misalignment compensation, and discuss how current trends in memory bandwidth and density are driving large-scale systems towards such solutions.