Title :
A shared built-in self-repair analysis for multiple embedded memories
Author :
Ohtani, Jun ; Ooishi, Tukasa ; Kawagoe, Tomoya ; Niiro, Mitsutaka ; Maruta, Masanao ; Hidaka, Hideto
Author_Institution :
ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A shared built-in self-repair analysis scheme (Shared-BISA) for multiple embedded memory cores in the SOC is proposed to realize minimum area penalty independent of the number of embedded memory cores. A compact reconfigurable CAM array in the BISA circuitry realizes a flexible redundancy analysis structure to cope with various memory core and redundancy structures, and a high-speed operation up to 500 MHz
Keywords :
DRAM chips; application specific integrated circuits; built-in self test; content-addressable storage; high-speed integrated circuits; reconfigurable architectures; redundancy; 500 MHz; SOC; Shared-BISA; compact reconfigurable CAM array; flexible redundancy analysis structure; high-speed operation; memory core; minimum area penalty; multiple embedded memories; shared built-in self-repair analysis; Algorithm design and analysis; Built-in self-test; CADCAM; Circuit testing; Computer aided manufacturing; Costs; Coupling circuits; Flexible printed circuits; Random access memory; Ultra large scale integration;
Conference_Titel :
Custom Integrated Circuits, 2001, IEEE Conference on.
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-6591-7
DOI :
10.1109/CICC.2001.929752
